Application of the latest generation of eopdh chip

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There is no doubt that the future is the era of all IP, but at present, the number of PDH network ports in the world is still very large, so how to successfully solve the network transition has become a major problem for operators and equipment manufacturers. Ethernet over PDH (eopdh) can transmit Ethernet services through PDH network, which has become an alternative solution to the problem of network convergence. Previous eopdh devices were mostly based on private protocols, so its application was limited to dedicated or point-to-point applications. The formulation of ITU-T g.7043 and g.8040 standards makes the interconnection between the new generation of eopdh devices possible. The new generation of eopdh technology can be a supplement to EOS in the wired field. Their joint deployment can realize the transmission of Ethernet on the existing copper cable; In the wireless field, the survey shows that PDH will still be retained in the future base stations. Because base stations and base station controllers must be connected to wired networks, and GFP, vcat and LCAS are all candidates for wired networks, the new generation of eopdh devices can be interconnected with them; At the same time, there is no Ethernet access device in some IP UTRAN areas. At this time, eopdh can provide Ethernet services as a temporary transition scheme. Compared with other convergence technologies, GFP and vcat are more efficient than PPP, ML-PPP and HDLC in many aspects such as latency and network availability

the main protocols and functional chips of eopdh

the ds33x series chips launched by Maxim can realize all the functions of eopdh by a single chip. The system design is simple and does not need complex peripheral circuits. For different applications, there are different options from single channel to 16 channel interfaces. Its performance exceeds that of the general radiation resistant material polystyrene case, and the hardware pins of each chip are compatible and the software architecture is consistent. Taking ds33x162 as an example, its block diagram is shown in Figure 1:

Figure 1: functional block diagram of ds33x series eopdh chip

it can be seen from Figure 1 that ds33x162 includes various functions required for eopdh protocol conversion, and realizes control and processing in hardware mode. Vcat/lcas, gfp/hdlc encapsulation and other processes do not require software development on the data path. For ds33w41 and ds33w11 in the series of chips, the integrated voice port makes them the best choice for IAD devices

the new generation of eopdh mainly involves the following protocols: g.7043 stipulates how to converge multiple circuits to a virtual channel, which is equivalent to the construction of the framework; G. When talking about the differences between domestic and foreign material suppliers, 7041 and g.8040 define how to package the payload into a specific frame format, which is equivalent to filling the content. G.7042 uses adding or removing some circuits to increase or decrease the size of the channel, which is equivalent to the adjustment of the internal capacity

packaging and mapping technology: the early eopdh packaging technology has no de facto standard. Traditionally, high-speed data link protocol (HDLC) and link access protocol (LAPS) on SDH are used as the packaging protocol of data packets. Therefore, many processing processes are defined by each chip manufacturer. When both ends are products of the same manufacturer, there will be no problem. But when it comes to different manufacturers, interconnection will become a major problem. General framing procedure (GFP) is a new packaging procedure, which belongs to ITU-T g.7041 specification. As a new option, it enables the interconnection of eopdh, EOS and MSTP from multiple manufacturers in the future

The protocol encapsulation of

gfp is mainly composed of three parts: core overhead area, payload area and optional payload area frame verification, which has relatively large flexibility. It uses header error control (HEC) technology to divide frames, which is similar to the method used in ATM. By judging the frame length of the payload length identification (PLI) field and the core Header Check Sequence (CHEC) field in the core frame header, the frame demarcation is completed by using the migration of three states: "search state", "pre homogait" and "homogait". The uh5000 series microcomputer controlled electronic universal testing machine is used for the static mechanical property test, analysis and research of metal and non-metallic materials in the normal temperature environment, such as tension, contraction, zigzag, shear, peel, tear, load retention and so on. It can automatically calculate the maximum force, maximum deformation, tensile strength, zigzag strength, compression strength, Reh, rel, Rp0.2, FM, Rt0.5, rt0.6, rt0.65, rt0.7, RM E and other experimental parameters. For other encapsulation protocols using start/stop tags (such as HDLC and laps), when there are start/stop tags in user data, longer escape sequences must be used to replace them, which usually leads to bandwidth expansion. Using HEC frame division technology, GFP does not need to replace flags in the data stream, which makes GFP achieve stable and predictable load throughput. In addition, using the scrambling mechanism GFP can maximally suppress the occurrence of pseudo data frames, and the error correction mechanism ensures that it can still work normally in case of error on the physical link, so GFP has very high reliability

the mapping process is to put the encapsulated Ethernet frame into a "container" to facilitate transmission on the link. The main purpose of containers is to align information. Containers usually have strict format definitions to monitor overhead and manage business at predetermined locations. Some containers also provide management/signaling paths and link quality monitoring functions. Different technologies have different names for these containers, and PDH includes DS1, E1, DS3 and E3 framing architecture. In most cases, one or more low rate containers can be formed, that is, mapped to a higher rate container

when the encapsulated Ethernet frame is uploaded on the PDH, the time between Ethernet frames is filled by a pair of blank numbers that play a significant role in abs+gf materials. ITU-T g.8040 standard defines four byte alignment rules for DS3 links. When GFP encapsulated frames are transmitted in DS1 or E1, the transmitted information is aligned by bytes, which is slightly more complex than DS3

ds33x162 supports various currently popular encapsulation protocols, including GFP-f, laps, HDLC and chdlc, and supports g.8040 GFP over PDH mapping protocol

link aggregation and adjustment: link aggregation is the process of integrating two or more physical links into a single virtual link, which is mainly used to increase the bandwidth between two network nodes and slow down the transmission to PDH or SDH branches. It is actually a structured method of allocating data on multiple signal channels, aligning the information received from different channels with different waiting times, and then recompiling the data and handing it over to the high-level protocol. Link aggregation is not a new technology. Multi link frame relay (mlfr), DSL binding technology, ATM reverse multiplexing (IMA) and multi link point-to-point (ML-PPP) protocols are all link aggregation technologies. Among them, IMA and mlfr are the most widely used. However, in all these schemes, each protocol can only play a single role under a specific background or frame format. Only PDH line binding technology perfectly solves the problem of Ethernet

at present, the main link aggregation technology used in sonet/sdh network is virtual concatenation (vcat) defined in ITU-T G.707 standard. This standard uses existing overhead channels as vcat overhead. However, when the vcat concept is applied to the PDH network, the existing management channel is not enough, and a new space needs to be allocated to the vcat overhead. In eopdh, the overhead bytes occupy the first time slot of each DS1 super extended frame that has been connected in series

the management channel created by the vcat overhead bytes will be used to transmit information about the link. For each transmitted DS1 super extended frame or E1 multiframe, each link will be attached with a vcat overhead byte. Therefore, 1/576 of the available bandwidth of DS1 will be used for vcat overhead

The low byte of the

vcat overhead byte includes the multiframe identifier (MFI), which is used to align frames with different transmission delay times. The high byte contains a unique controller (all 16 values of the multiframe indicator). This high byte is called VLI and contains virtual concatenation and link capacity adjustment mechanism (LCAS) information

cascaded links are also called virtual concatenation (VCG), and all members of the virtual concatenation have their own vcat overhead channels. ITU-T g.7043 standard specification introduces the complete eopdh link aggregation specification

lcas provides an adaptation function between the source and destination of virtual concatenation, allowing dynamic changes in bandwidth without causing service loss, that is, a control mechanism that changes the line capacity without damage, which is used to increase or reduce the capacity of containers formed by virtual concatenation in communication. Link capacity adjustment adjusts aggregate throughput by adding or deleting logical links between two nodes. When adding or deleting members of virtual level federations, the two end nodes use LCAS to negotiate. LCAS uses vcat overhead channels to perform negotiation functions. With the help of LCAS, the bandwidth of virtual concatenation can be increased without interrupting the data flow. In addition, the faulty link will be automatically deleted to minimize the impact on the service. The complete standard of LCAS is detailed in ITU-T g.7042/y.1305

ds33x162 has the ability of vcatlcas convergence for 16 links

vlan and priority: VLAN forwarding is mainly used to distribute or aggregate data traffic, and priority scheduling is used to set priority for data waiting in the WAN transmission queue, so that when there is free bandwidth, high-level data can be sent first. Priority scheduling and priority forwarding are different. Priority forwarding is mainly used to place data with different priorities on different Wan physical connections. Whether VLAN forwarding or priority scheduling and forwarding are determined by the forwarding mode of the chip. It should be noted that priority does not provide a good path for high priority business data. In fact, priority and scheduling only allow "more important" business data to be transmitted earlier at the buffer node. Good service quality should also take into account other factors

ds33x162 series chips support VLAN forwarding and priority scheduling/forwarding of VLAN 802.1p and DSCP. At the same time, it supports congestion avoidance and congestion management functions. Congestion avoidance information is built into CIR, and congestion management information adopts Ethernet flow control mechanism

oam: in Carrier Ethernet, operation, management and maintenance (OAM) is used to transmit management messages, such as the status between two network nodes, report faults and test connectivity. It can reduce the burden of network operation, test network performance and reduce operation cost. Because OAM will automatically detect the performance degradation or failure of the network, OAM is closely related to the service level that users can get

the message transmitted is called OAM protocol data unit (OAMPDU). The industry has defined 16 OAM protocol data units for different purposes. IEEE, ITU and MEF have jointly stipulated the format and usage of OAM protocol data unit. Relevant standards include IEEE 802.3ah and 802.3ag, and ITU-T y.1731 and y.1730

whether from WAN port or LAN port, ds33x162 series chips can use the main processor to insert and extract frames, and the processor can use this method to manage OAM and Ethernet services. The four user readable FIFOs set for this purpose will send interrupts when they are empty (insert FIFO) or have frames (extract FIFO). The maximum frame that the chip can capture or insert is 2048byte

for QoS and OAM frame extraction, ds33x162 supports a total of six frame formats, but users do not need to formulate or configure an Ethernet frame format, because usually LAN data contains many different Ethernet formats at the same time

group example

eopdh embedded system should generally include the following three parts: Ethernet interface part, protocol conversion part and PDH interface part, as shown in Figure 2. Wherein ether

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